// $Id: RandomLfsrC.nc,v 1.5 2010-06-29 22:07:56 scipio Exp $

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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * Copyright (c) 2002-2005 Intel Corporation
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/*
 *
 * Authors:		Alec Woo, David Gay, Philip Levis
 * Date last modified:  8/8/05
 *
 */

/**
 * This is a 16 bit Linear Feedback Shift Register pseudo random number
   generator. It is faster than the MLCG generator, but the numbers generated
 * have less randomness.
 *
 * @author Alec Woo
 * @author David Gay
 * @author Philip Levis
 * @date   August 8 2005
 */

module RandomLfsrC
{
  provides interface Init;
  provides interface Random;
}
implementation
{
  uint16_t shiftReg;
  uint16_t initSeed;
  uint16_t mask;

	/** 
	* Initialize the pseudorandom generator with a specific seed. 
	* @return void.
	*/
	async command void Random.setSeed(uint16_t seed)
	{
		atomic
		{
			if (seed == 0)
			{
				// Use TOS_NODE_ID
				shiftReg = 119 * 119 * (TOS_NODE_ID + 1);
				initSeed = shiftReg;
				mask = 137 * 29 * (TOS_NODE_ID + 1);
			}
			else
			{
				// Use seed
				shiftReg = 119 * 119 * (seed + 1);
				initSeed = shiftReg;
				mask = 137 * 29 * (seed + 1);
			}
		}
	}


  /* Initialize the seed from the ID of the node */
  command error_t Init.init() {
    atomic {
      shiftReg = 119 * 119 * (TOS_NODE_ID + 1);
      initSeed = shiftReg;
      mask = 137 * 29 * (TOS_NODE_ID + 1);
    }
    return SUCCESS;
  }

  /* Return the next 16 bit random number */
  async command uint16_t Random.rand16() {
    bool endbit;
    uint16_t tmpShiftReg;
    atomic {
      tmpShiftReg = shiftReg;
      endbit = ((tmpShiftReg & 0x8000) != 0);
      tmpShiftReg <<= 1;
      if (endbit) 
	tmpShiftReg ^= 0x100b;
      tmpShiftReg++;
      shiftReg = tmpShiftReg;
      tmpShiftReg = tmpShiftReg ^ mask;
    }
    return tmpShiftReg;
  }

  async command uint32_t Random.rand32() {
    return (uint32_t)call Random.rand16() << 16 | call Random.rand16();
  }
}
